The present invention relates to integrated circuits and fabrication techniques for forming interpoly dielectric stacks used in flash memory technology. More particularly, the present invention relates to integrated circuits and fabrication techniques for forming xe2x80x9cONOxe2x80x9d interpoly dielectric stacks used in flash memory technology. Even more particularly, the present invention relates to integrated circuits and fabrication techniques for forming the bottom oxide layer of an xe2x80x9cONOxe2x80x9d interpoly dielectric stack used in flash memory technology.
The current state of the art in flash memory technology uses an interpoly dielectric stack typically consisting of the following layers: silicon dioxide (bottom), silicon nitride (middle), and silicon dioxide (top), known as an xe2x80x9cONOxe2x80x9d (hereinafter referred to as ONO). The thickness of the ONO stack ranges from 100 xc3x85 to 300 xc3x85, assuming a dielectric constant of 3.7 for the entire dielectric stack. The top oxide layer of the ONO stack is typically formed by thermal growth in an ambient steam. The middle nitride layer of the ONO stack is typically thinned during the formation of the top oxide layer. The bottom oxide layer of the ONO stack is exposed to the conditions arising from the formation of these two upper layers of the ONO stack. Accordingly, the electrical integrity of the bottom oxide layer is extremely critical to device performance. The thinning action acting on the previously formed oxide or nitride layer of the ONO stack introduces a problem: unreliable thickness determination of the completed ONO stack.
While U.S. Pat. Nos. 5,166,904 and 4,758,986 disclose texture asperities and roughness on polysilicon surfaces for the purpose of creating asymmetry in the structure to affect the electron tunneling and the magnitude of the tunneling threshold voltage, to Applicants"" knowledge, no known flash memory fabrication process exists for forming nor flash memory structure exists having a polysilicon layer treated to form a protective layer prior to formation of the interpoly dielectric stack such that the subsequently formed interpoly dielectric stack""s characteristics are optimized and improved, notwithstanding any adverse thinning action caused by the dielectric stack fabrication process. Further, no known flash memory fabrication process exists for forming nor flash memory structure exists, so formed, which both improves the reliability of the bottom oxide layer of an ONO interpoly dielectric stack and facilitates decreasing thickness of an ONO stack, thereby resulting in capacitor coupling ratio changes of the flash memory element and, therefore, allowing the use of new power supply and programming voltages.
Accordingly, the present invention provides a flash memory structure having a polysilicon layer treated to form a protective layer prior to formation of the interpoly dielectric stack, such that the subsequently formed interpoly dielectric stack has optimized and improved characteristics, notwithstanding any adverse thinning action introduced by the subsequent dielectric stack fabrication process. The present invention also provides a fabrication process for forming a flash memory structure having a polysilicon layer treated to form a protective layer prior to formation of the interpoly dielectric stack, such that the subsequently formed interpoly dielectric stack has optimized and improved characteristics, notwithstanding any adverse thinning action caused by the dielectric stack fabrication process.
In particular, the flash memory structure of the present claimed invention is formed via a fabrication process, whereby stacks, of a first poly-crystalline silicon material or an amorphous silicon material being formed and processed to have an underlying thin film of silicon dioxide (i.e., at a partially formed stage of a memory element), are further processed to form a xe2x80x9cpre-interpoly dielectric treatment layer,xe2x80x9d in accordance with the teachings of the present claimed invention. The treatment layer is hereinafter termed a pre-interpoly dielectric treatment layer to distinguish it from a post-treatment layer taught in Applicants"" co-pending related U.S. patent application, Ser. No. 60,148,946, entitled xe2x80x9cFLASH MEMORY HAVING A TREATMENT LAYER INTERPOSED BETWEEN AN INTERPOLY DIELECTRIC AND METHOD OF FORMING,xe2x80x9d referenced by Assignee""s internal number D928, and hereby incorporated by reference.
This pre-interpoly dielectric treatment layer, in accordance with the present invention, involves exposing the polysilicon stacks to a selected ambient reagent gas of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the polysilicon stacks to such selected ambient reagent gases is performed in a fabrication tool such as a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber. The at least three ambient reagent gases are grouped in an ambient reagent gas group consisting essentially of: (1) nitrous oxide (N2O) and/or nitric oxide (NO), (2) oxygen (O2) and/or water (H2O), and (3) ammonia (NH3). Any one ambient reagent gas may be selected and utilized in any of the foregoing fabrication tools for pre-treating the surface of the first polysilicon stack prior to forming the interpoly dielectric structure member of the flash memory element. Other features of the present invention are disclosed, or are apparent in the section entitled xe2x80x9cDETAILED DESCRIPTION OF THE INVENTION.xe2x80x9d